This invention relates to CMOS VLSI Circuits and in particular to an output driver having precise control of the rise and fall times of the signals generated from such driver.
The transmission of a digital signal over an interconnect structure wherein the inherent signal's rise and fall times are comparable to or less than the signal propagation time along the interconnect from a source to a destination presents a problem traditionally referred to as the "edge-speed" problem. In the past, this effect was associated with a few selected high-speed, digitial circuit device technologies such as emitter-coupled logic (ECL). However, as all device technologies are being produced with ever shrinking physical dimensions, their associated speed of response is becoming much faster.
For high-speed digital communication, the traditional approach has been to transmit the digital signals over "transmission-line" interconnects possessing a controlled wave impedance. This approach necessitates the incorporation of line termination resistors to match the line wave impedance--typically 50-70 ohms. For general high speed VLSI circuit chips having as many as 100-200 I/O connections, this becomes a physically difficult task. Not only is it physically difficult, but it results in a significant power dissipation in the chip driver (within the chip). If line matching is not used, then undesireable "ringing" will be experienced at either or both the sending end (driver output) or receiving end (chip input). This is the result of reflections at the receiving and sending ends (or at other points of discontinuity) due to the impedance mismatching. In some cases, when the interconnect length is "short" relative to the signal rise and fall times, "wave" effects are minimal, and hence, impedance matching is not required.
In U.S. Pat. No. 4,414,480 issued to John J. Zasio on Nov. 8, 1983 it discloses that ECL circuitry generally utilizes one volt signal swings, and transmission lines having a 100 ohm characteristic impedance are typically used to provide interconnection between integrated circuit chips. CMOS technology has several advantages over ECL which makes it particularly attractive for use in high speed computers; primary among these is the fact that CMOS circuits consume little or no D.C. power, i.e. power is required only when the circuit is switching. However, CMOS circuits typically have a five volt signal swing and would have to provide a 50 milliamp drive current to drive a 100 ohm transmission line on a chip resulting in a requirement of 250 milliwatts per output line. Because of this excessive power requirement, transmission lines have not been used for interconnection between CMOS chips.
Zasio further discloses a CMOS output circuit for driving either a nonterminated transmission line, a terminated transmission line or a random wire ffor relatively short distances) while achieving both low power consumption and high speed. Such output circuit is designed to have its output impedance approximately equal to the characteristic impedance of a transmission line. Also, a receiver circuit is provided which appears as an open circuit connection to a transmission line resulting in a CMOS output circuit which only has to provide one-half the signal swing required by the receiving circuit; this significantly reduces the drive current requirements of the output circuit. This approach satisfies the case of a simple single source to a single destination; however, a matrix of interconnection I/O lines cannot be accommodated in this manner.